05425036 is referenced by 247 patents and cites 23 patents.

An improved electronic design automation (EDA) system employs field programmable gate arrays (FPGAs) for emulating prototype circuit designs. A circuit netlist file is down-loaded to the FPGAs to configure the FPGAs to emulate a functional representation of the prototype circuit. To check whether the circuit netlist is implemented properly, the FPGAs are tested functionally by applying input vectors thereto and comparing the resulting output of the FPGAs to output vectors provided from prior simulation. If the FPGAs fail such vector comparison, the FPGAs are debugged by inserting "read-back" trigger instructions in the input vectors, preferably corresponding to fail points in the applied vector stream. Modifying the input vectors with such read-back signals causes the internal states of latches and flip-flops in each FPGA to be captured when functional testing is repeated. Such internal state information is useful for debugging the FPGAs, and particularly convenient because no recompilation of the circuit netlist is required. A similar approach which also uses the read-back feature of FPGAs is employed to debug FPGAs coupled to a target system which appears to fail during emulation runs.

Title
Method and apparatus for debugging reconfigurable emulation systems
Application Number
7/947308
Publication Number
5425036
Application Date
September 18, 1992
Publication Date
June 13, 1995
Inventor
Kenneth S K Choi
San Jose
CA, US
Thomas B Huang
San Jose
CA, US
Jeong Tyng Li
Cupertino
CA, US
Dick L Liu
Saratoga
CA, US
Agent
Lyon & Lyon
Assignee
Quickturn Design Systems
CA, US
IPC
G06F 15/60
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