05404469 is referenced by 144 patents and cites 2 patents.

A static interleaving technique solves the problem of resource contention in a very long instruction word multi-threaded microprocessor architecture. In the static interleaving technique, each function unit in the processor is allocated for the execution of an instruction from a particular thread in a fixed predetermined time slot in a repeating pattern of predetermined time slots. The fixed predetermined pattern of time slots represents the resource constraints imposed on the hardware to resolve the contention for computing resources among the instruction threads. The strategy of resource allocation is exposed to a parallel compiler which organizes a sequence of instructions into the horizontal instruction words which form each thread so as to maintain the data dependencies among the instructions and to take into account the fixed predetermined allocation of hardware resources.

Title
Multi-threaded microprocessor architecture utilizing static interleaving
Application Number
7/840903
Publication Number
5404469
Application Date
February 25, 1992
Publication Date
April 4, 1995
Inventor
Chuan Lin Wu
Austin
TX, US
Jin Chin Chung
Hsinchu
TW
Agent
Meltzer Lippe Goldstein Wolf Schlissel & Sazer
Assignee
Industrial Technology Research Institute
TW
IPC
G06F 9/38
G06F 9/30
G06F 9/24
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