05404338 is referenced by 132 patents and cites 3 patents.

In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in word line shunt regions (WS). The connection switches (BS) are arranged in the crossing between the local I/O line pairs and global I/O line pairs. Each small memory array in the activated memory array is connected to the corresponding global I/O line pair through the local I/O line pair. Thereby, a plurality of bits can be simultaneously read without increasing an area occupied by interconnections. The control of connection switch is made using a sense amplifier activation signal. Global I/O lines are precharged/equalized after data are transferred to read data registers provided for data output terminal for sequential data output or into selected memory cells. External clock signal is frequency-divided to produce phase-shifted internal clock signals which are used for producing internal voltage through charge operation.

Title
Synchronous type semiconductor memory device operating in synchronization with an external clock signal
Application Number
8/189247
Publication Number
5404338
Application Date
January 31, 1994
Publication Date
April 4, 1995
Inventor
Seiji Sawada
Hyogo
JP
Naoya Watanabe
Hyogo
JP
Yasuhiro Konishi
Hyogo
JP
Hisashi Iwamoto
Hyogo
JP
Yasumitsu Murai
Hyogo
JP
Agent
Lowe Price LeBlanc & Becker
Assignee
Mitsubishi Electric Engineering
JP
Mitsubishi Denki Kabushiki Kaisha
JP
IPC
G11C 13/00
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