05388224 is referenced by 40 patents and cites 15 patents.

A computer system including a plurality of processors and a bus coupling the processors to one another via respective bus interfaces. The bus includes a plurality of slots for coupling the interfaces to the bus. Each interface includes an ID register coupled to the interface device, the ID register containing identification information unique to the slot of the bus used to couple the respective interface to the bus. The interface device is responsive to an address command cycle of the bus to place the identification information from the ID register on the bus during a READ bus transaction initiated by the interface and directed to another slot of the bus. A processor requiring identification of the corresponding slot causes the respective interface to initiate a READ bus transaction directed to another slot of the bus. The bus is operated so that the module at the slot to which the READ transaction is directed, returns the slot identification information to the initiator interface for communication to the corresponding processor.

Title
Processor identification mechanism for a multiprocessor system
Application Number
7/873924
Publication Number
5388224
Application Date
April 24, 1992
Publication Date
February 7, 1995
Inventor
Barry A Maskas
Sterling
MA, US
Agent
Denis G Maloney
Albert P Cefalo
Assignee
Digital Equipment Corporation
MA, US
IPC
G06F 13/00
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