05384476 is referenced by 104 patents and cites 7 patents.

A semiconductor device having a source region, a drain region and a channel region which are formed in a surface portion of a semiconductor substrate, and a gate formed with a material having a relatively high built-in voltage relative to the source region. This semiconductor device may further include, in the semiconductor substrate to extend along the channel region, a highly-doped region having a conductivity type opposite to that of the source region. This highly-closed region may have an impurity concentration gradient which is greater toward its portion facing the abovesaid surface of the substrate. These arrangements serve to prevent extinction of memory due to current leakage during absence of bias voltage which otherwise would develop in semiconductor devices having short-channel and thin gate oxide layer, and due to irradiation of alpha-particle onto the device.

Title
Short channel MOSFET with buried anti-punch through region
Application Number
179782
Publication Number
5384476
Application Date
June 9, 1987
Publication Date
January 24, 1995
Inventor
Tadahiro Ohmi
Sendai
JP
Jun ichi Nishizawa
Sendai
JP
Agent
Cushman Darby & Cushman
Assignee
Zaidan Hojin Handotai Kenkyu Shinkokai
JP
IPC
H01L 27/108
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