05371864 is referenced by 51 patents and cites 26 patents.

A data processing apparatus for simultaneously reading out groups of two or more contiguous, variable length instructions from memory, and for decoding the group of variable length instructions in parallel. The data processing apparatus has a memory containing at least first, second, and third contiguous instructions, and at least first, second, and third read ports for receiving starting addresses and for reading out the instructions from the memory. A next instruction pointer supplies the starting address of the first instruction to the first read port, receives the first instruction, decodes the length of the first instruction, determines the starting address of the second instruction, supplies the starting address of the second instruction to the first read port, receives the second instruction, decodes the length of the second instruction, and determines the starting address of the third instruction. All of these operations are performed in one cycle time. An instruction pointer queue receives and stores the starting addresses of at least the second and third instructions, and supplies the starting addresses to the second and third read ports for simultaneously reading out the second and third instructions from the memory. First and second instruction decoders receive and simultaneously decode the second and third instructions.

Title
Apparatus for concurrent multiple instruction decode in variable length instruction set computer
Application Number
7/866766
Publication Number
5371864
Application Date
April 9, 1992
Publication Date
December 6, 1994
Inventor
Chiao Mei Chuang
Briarcliff Manor
NY, US
Agent
Robert P Tassinari Jr
Marc D Schechter
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 9/32
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