05357617 is referenced by 96 patents and cites 11 patents.

A hybrid pipelined processor and associated processing methods are described for separately handling substantially concurrently in a time division manner multiple program instruction threads. The hybrid architecture includes an instruction fetch unit, an instruction decode unit and an execution unit. The execution unit includes multiple sets of register files each of which contains the working contents for a corresponding one of a plurality n of instruction threads. Timing and control circuitry is coupled to each of the principal processor components for controlling the timing and sequence of operations on instructions from the plurality n of instruction threads such that multiple instruction threads are separately handled substantially concurrently. Corresponding hybrid processing methods for such a single pipelined processor are also discussed.

Title
Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor
Application Number
7/796194
Publication Number
5357617
Application Date
November 22, 1991
Publication Date
October 18, 1994
Inventor
Sebastian Ventrone
Jericho
VT, US
Gordon T Davis
Raleigh
NC, US
Agent
Heslin & Rothenberg
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 9/40
G06F 9/38
G06F 9/00
View Original Source