05355467 is referenced by 136 patents and cites 12 patents.

A second level cache memory controller, implemented as an integrated circuit unit, operates in conjunction with a secondary random access cache memory and a main memory (system) bus controller to form a second level cache memory subsystem. The subsystem is interfaced to the local processor (CPU) bus and to the main memory bus providing independent access by both buses, thereby reducing traffic of the main memory bus when the data required by the CPU is located in secondary cache. Similarly, CPU bus traffic is minimized when secondary cache access by the main memory bus for snoops and write-backs to main memory. Snoop latches interfaced with the main memory bus provide snoop access to the cache memory via the cache directory in the secondary cache controller unit. The controller also supports parallel look-up in the controller tag array and the secondary cache using most-recently-used (MRU) main memory write-through and pipelining of memory bus cycle requests.

Title
Second level cache controller unit and system
Application Number
710507
Publication Number
5355467
Application Date
March 8, 1994
Publication Date
October 11, 1994
Inventor
Itzik Silas
Haifa
IL
Adalberto Golbert
Haifa
IL
Robert L Farrell
Portland
OR, US
Peter D MacWilliams
Aloha
OR, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Intel Corporation
CA, US
IPC
G06F 13/00
View Original Source