05355460 is referenced by 91 patents and cites 7 patents.

A digital computer system capable of processing two or more computer instructions in parallel and having a main memory unit for storing information blocks including the computer instructions includes an instruction compounding unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with another neighboring instruction. Tagged instructions are stored in the main memory. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to the functional units are obtained from the memory by way of a cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.

Title
In-memory preprocessor for compounding a sequence of instructions for parallel computer system execution
Application Number
543464
Publication Number
5355460
Application Date
July 29, 1993
Publication Date
October 11, 1994
Inventor
Bartholomew Blaner
Newark Valley
NY, US
Stamatis Vassiliadis
Vestal
NY, US
Richard J Eickemeyer
Endicott
NY, US
Agent
Terrance A Meador
Lynn L Augspurger
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 9/40
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