05337266 is referenced by 7 patents and cites 13 patents.

An apparatus is provided for logarithmic subtraction that is suitable for general purpose computing using the sign logarithm number system. In the sign logarithm number system, a sign bit is concatenated to a fixed point approximation of the logarithm of the absolute value of the real number being represented. Multiplication and division are easy and fast because the only steps required are to add or subtract the logarithms and exclusive OR the sign bits. In the prior art, logarithmic arithmetic has been restricted to limited precision applications (8-16 bits), such as digital filtering, because of the problem of accurate, high speed subtraction. The present invention provides a new circuit for subtracting two numbers represented in logarithmic form which makes design of arithmetic units for larger word sizes (32 bits) practical. The subtraction circuit approximates log.sub.b .vertline.1-b.sup.z .vertline., where z is the difference of the logarithms being subtracted. The value of z is shifted, and the high part of z is used as input to two ROMs. The output of the first ROM is added to the product of the second ROM and the low part of the shifted z value. In the case of z being close to zero, the low part of z is used as input to a third ROM, which provides a more accurate approximation of log.sub.b .vertline.1-b.sup.z .vertline..

Title
Method and apparatus for fast logarithmic addition and subtraction
Application Number
135676
Publication Number
5337266
Application Date
April 10, 1990
Publication Date
August 9, 1994
Inventor
Mark G Arnold
1400 Grand Ave., Laramie, 82070
WY, US
Agent
William E Hein
IPC
G06F 15/00
G06F 7/00
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