05335335 is referenced by 54 patents and cites 12 patents.

A method and apparatus for enabling a dual ported cache system in a multiprocessor system to guarantee snoop access to all host bus cycles which require snooping. The cache controller includes a set of latches coupled to the host bus which it uses to latch the state of the host bus during a snoop cycle if the cache controller is unable to immediately snoop that cycle. The cache controller latches that state of the host bus in the beginning of a cycle and preserves this state throughout the cycle due to the effects of pipelining on the host bus. In addition, the cache controller is able to delay host bus cycles to guarantee snoop access to host bus cycles which require snooping. The cache controller generally only delays a host bus cycle when it is already performing other tasks, such as servicing its local processor, and cannot snoop the host bus cycle immediately. When the cache controller latches the state of the bus during a write cycle, it only begins to delay the host bus after a subsequent cycle begins. In this manner, one write cycle can complete on the host bus before the cache controller delays any cycles, thereby reducing the impact of snooping on host bus bandwidth. Read cycles are always delayed until the cache controller can complete the snooping operation because the cache may be the owner of the data and a write back cycle may be necessary.

Title
Multiprocessor cache snoop access protocol wherein snoop means performs snooping operations after host bus cycle completion and delays subsequent host bus cycles until snooping operations are completed
Application Number
7/753420
Publication Number
5335335
Application Date
August 30, 1991
Publication Date
August 2, 1994
Inventor
Roger E Tipley
Houston
TX, US
Jeffrey C Stevens
Spring
TX, US
Mike T Jackson
Houston
TX, US
Agent
Pravel Hewitt Kimball & Krieger
Assignee
Compaq Computer Corporation
TX, US
IPC
G06F 12/00
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