05334952 is referenced by 120 patents and cites 9 patents.

A phase locked loop including a switch between a phase detector output and a VCO input to open the PLL during a frequency change is provided. While the PLL is open, an analog error correction signal is generated by sampling any residual error coming from the phase detector, and generating the analog error correction signal to counter the residual error. Once analog error correction signal is available, the switch is closed and the error correction signal is added to the phase detector output and the PLL is allowed to settle to an optimized frequency.

Title
Fast settling phase locked loop
Application Number
8/38147
Publication Number
5334952
Application Date
March 29, 1993
Publication Date
August 2, 1994
Inventor
Graeme S Paterson
Boulder
CO, US
Steven L Maddy
Boulder
CO, US
Agent
Dorr Carson Sloan & Peterson
Assignee
SpectraLink Corporation
CO, US
IPC
H03L 7/16
H03L 7/10
H03L 7/085
H03L 7/08
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