05327570 is referenced by 78 patents and cites 17 patents.

A multiprocessor data processing system (10), and a method of operating same, so as to provide efficient bandwidth utilization of shared system resources (24, 26). The system includes a plurality of processor nodes, each of which includes a data processor (22a, 28a). A first step of a method buffers data written by a data processor to a first bus (23a), prior to the data being transmitted to a second bus (32). Also buffered are byte enable (BE) signals generated by the data processor in conjunction with the data written by the data processor. A next step performs a main memory (26) write operation by transmitting the buffered data to the second bus; responsive to the stored BE signals, also transmitting a control signal for indicating if a memory write is to be accomplished as a read-modify-write (RMW) type of memory operation; and transmitting the stored BE signals to the second bus. A further step couples the data, the RMW signal, and the BE signals from the second bus to a third bus (24) for reception by the main memory.

Title
Multiprocessor system having local write cache within each data processor node
Application Number
7/734432
Publication Number
5327570
Application Date
July 22, 1991
Publication Date
July 5, 1994
Inventor
Robert B Pearson
Cold Spring
NY, US
Armando Garcia
Yorktown Heights
NY, US
David J Foster
White Plains
NY, US
Agent
Perman & Green
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 9/00
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