05325504 is referenced by 90 patents and cites 9 patents.

A method and apparatus for incorporating cache line replacement and cache write policy information into the tag directories in a cache system. In a 2 way set-associative cache, one bit in each way's tag RAM is reserved for LRU information, and the bits are manipulated such that the Exclusive-OR of each way's bits points to the actual LRU cache way. Since all of these bits must be read when the cache controller determines whether a hit or miss has occurred, the bits are available when a cache miss occurs and a cache line replacement is required. The method can be generalized to caches which include a number of ways greater than two by using a pseudo-LRU algorithm and utilizing group select bits in each of the ways to distinguish between least recently used groups. Cache write policy information is stored in the tag RAM's to designate various memory areas as write-back or write-through. In this manner, system memory situated on an I/O bus which does not recognize inhibit cycles can have its data cached.

Title
Method and apparatus for incorporating cache line replacement and cache write policy information into tag directories in a cache system
Application Number
7/752761
Publication Number
5325504
Application Date
August 30, 1991
Publication Date
June 28, 1994
Inventor
Philip C Kelly
Houston
TX, US
Roger E Tipley
Houston
TX, US
Agent
Pravel Hewitt Kimball & Krieger
Assignee
Compaq Computer Corporation
TX, US
IPC
G06F 12/02
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