05317720 is referenced by 114 patents and cites 13 patents.

A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. A writeback cache is used (instead of writethrough) in a hierarchical cache arrangement, and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. Separate queues are provided for the return data from memory and cache invalidates, yet the order or bus transactions is maintained by a pointer arrangement. The bus protocol used by the CPU to communicate with the system bus is of the pended type, with transactions on the bus identified by an ID field specifying the originator, and arbitration for bus grant goes one simultaneously with address/data transactions on the bus.

Title
Processor system with writeback cache using writeback and non writeback transactions stored in separate queues
Application Number
547699
Publication Number
5317720
Application Date
March 22, 1993
Publication Date
May 31, 1994
Inventor
Raymond Strouble
Southbridge
MA, US
Samyojita Nadkarni
Shrewsbury
MA, US
David Archer
Marlborough
MA, US
John Edmondson
Somerville
MA, US
Rebecca L Stamm
Boston
MA, US
Agent
Denis G Maloney
Richard J Paciulan
Assignee
Digital Equipment Corporation
MA, US
IPC
G06F 13/00
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