05303362 is referenced by 116 patents and cites 24 patents.

A coherent coupled memory multiprocessor computer system that includes a plurality of processor modules (11a, 11b . . . ), a global interconnect (13), an optional global memory (15) and an input/output subsystem (17,19) is disclosed. Each processor module (11a, 11b . . . ) includes: a processor (21); cache memory (23); cache memory controller logic (22); coupled memory (25); coupled memory control logic (24); and a global interconnect interface (27). Coupled memory (25) associated with a specific processor (21), like global memory (15), is available to other processors (21). Coherency between data stored in coupled (or global) memory and similar data replicated in cache memory is maintained by either a write-through or a write-back cache coherency management protocol. The selected protocol is implemented in hardware, i.e., logic, form, preferably incorporated in the coupled memory control logic (24) and in the cache memory controller logic (22). In the write-through protocol, processor writes are propagated directly to coupled memory while invalidating corresponding data in cache memory. In contrast, the write-back protocol allows data owned by a cache to be continuously updated until requested by another processor, at which time the coupled memory is updated and other cache blocks containing the same data are invalidated.

Title
Coupled memory multiprocessor computer system including cache coherency management protocols
Application Number
7/673766
Publication Number
5303362
Application Date
March 20, 1991
Publication Date
April 12, 1994
Inventor
Kenneth D Abramson
Seattle
WA, US
David A Orbits
Redmond
WA, US
H Bruce Butts Jr
Redmond
WA, US
Agent
Christensen O Connor Johnson & Kindness
Assignee
Digital Equipment Corporation
MA, US
IPC
G06F 12/06
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