05301344 is referenced by 124 patents and cites 8 patents.

A reconfigurable sequential processor includes a data bank for storing data to be processed; a programmable logic block address generator for addressing data in the data bank; a programmable logic block arithmetic unit responsive to the data bank for processing the data addressed by the programmable logic block address generator; an address generator hardware configuration file having a plurality of configuration files for configuring the programmable logic block address generator in one of a plurality of addressing configurations in response to an address operational code; an arithmetic hardware configuration file having a plurality of configuration files for configuring the programmable logic block arithmetic unit in one of a plurality of processing configurations in response to an arithmetic operational code; and for delivering a series of operational codes to each configuration file for enabling the programmable logic block address generator and the programmable logic block arithmetic unit to be configured to perform sequentially a corresponding series of arithmetic logic operations on the data in the data bank.

Title
Multibus sequential processor to perform in parallel a plurality of reconfigurable logic operations on a plurality of data sets
Application Number
7/647557
Publication Number
5301344
Application Date
January 29, 1991
Publication Date
April 5, 1994
Inventor
Alexander Kolchinsky
Andover
MA, US
Agent
Joseph S Iandiorio
Assignee
Analogic Corporation
MA, US
IPC
G06F 13/00
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