05297269 is referenced by 177 patents and cites 20 patents.

A cache coherency protocol for a multi-processor system which provides for read/write, read-only and transitional data states and for an indication of these states to be stored in a memory directory in main memory. The transitional data state occurs when a processor requests from main memory a data block in another processor's cache and the request is pending completion. All subsequent read requests for the data block during the pendency of the first request are inhibited until completion of the first request. Also provided in the memory directory for each data block is a field for identifying the processor which owns the data block in question. Data block ownership information is used to determine where requested owned data is located.

Title
Cache coherency protocol for multi processor computer system
Application Number
514716
Publication Number
5297269
Application Date
May 24, 1993
Publication Date
March 22, 1994
Inventor
Douglas Williams
Pepperel
MA, US
David M Robinson
Bellevue
WA, US
John M Parchem
Seattle
WA, US
David A Orbits
Redmond
WA, US
Mark N Howard
Issaquah
WA, US
Darrel D Donaldson
Lancaster
MA, US
Agent
Kenyon & Kenyon
Assignee
Digital Equipment Company
MA, US
IPC
G06F 12/00
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