05293603 is referenced by 65 patents and cites 19 patents.

An integrated circuit, for use as a cache subsystem, implements a cache static random access memory (SRAM) storage array, a central processor unit (CPU) bus interface and a main memory bus interface. The CPU bus and main memory bus interfaces include multiplexers, buffers, and local control for optimizing burst read and write operations to and from the CPU bus. These circuits allow a full cache line to be read or written in a single access of the SRAM array. Control logic is utilized within the CPU bus interface for controlling CPU bursts in the order defined by the CPU. The memory bus interface includes internal buffers used in performing memory bus reads, write-throughs, write-backs and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparently passing data between the CPU and memory bus interfaces without disturbance of the SRAM array.

Title
Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path
Application Number
7/710079
Publication Number
5293603
Application Date
June 4, 1991
Publication Date
March 8, 1994
Inventor
Robert L Farrell
Portland
OR, US
Clair C Webb
Aloha
OR, US
Peter D MacWilliams
Aloha
OR, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Intel Corporation
CA, US
IPC
G06F 12/08
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