05287484 is referenced by 25 patents and cites 5 patents.

A non-shared system with respect to an outside and an inside cache in a multi-processor system has multi-layer hierarchical cache. An invalidation address on a main memory address bus 31 in company with the rewriting of a main memory 30 is transmitted via a first and a second path 35, 36 to inside caches 11,21 so as to invalidate these inside caches 11, 21. The invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and outside caches 12, 22 so as to invalidate these outside caches 12, 22. It is extremely improbable for the address of access for writing to the transmitted to the main memory address bus 31 because the outside caches 12, 22 are operated in either copy back or write once system. As a result, even though the invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and the outside caches 12, 22, it is extremely improbably for the address of access for writing to conflict with a signal on the bidirectional connection.

Title
Multi-processor system for invalidating hierarchical cache
Application Number
540860
Publication Number
5287484
Application Date
November 13, 1992
Publication Date
February 15, 1994
Inventor
Yasuhiko Saigou
Fuchu
JP
Takashi Kikuchi
Akishima
JP
Hirokazu Aoki
Hachioji
JP
Kunio Uchiyama
Hachioji
JP
Osamu Nishii
Kokubunji
JP
Agent
Fay Sharpe Beall Fagan Minnich & McKee
Assignee
Hitachi VLSI Engineering
JP
Hitachi
JP
IPC
G06F 12/08
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