05283761 is referenced by 127 patents and cites 5 patents.

A method of processing data having one of four voltage levels stored in a DRAM cell is comprised of sensing whether or not the data voltage is above or below a voltage level midway between a highest and a lowest of the four levels, setting the voltage on a reference line higher than the lowest and lower than the next highest of the four levels in the event the data voltage is below the midway voltage level, and setting the voltage on the reference line higher than the second highest and lower than the highest of the four levels in the event the data voltage is above the midway point, and sensing whether the data voltage is higher or lower than the reference line, whereby which of the four levels the data occupies is read.

Title
Method of multi-level storage in DRAM
Application Number
7/916673
Publication Number
5283761
Application Date
July 22, 1992
Publication Date
February 1, 1994
Inventor
Peter B Gillingham
Kanata
CA
Agent
Antonelli Terry Stout & Kraus
Assignee
Mosaid Technologies Incorporated
CA
IPC
G11C 7/00
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