05283201 is referenced by 116 patents and cites 10 patents.

A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed areas (46) as stripes or a matrix, and protected areas. Sidewall spacers (44) of predetermined thickness (52) with inner surfaces (48) contact the protective layer sidewalls. A first trench (50) is formed in substrate areas (46) with sidewalls aligned to the sidewall spacer outer surfaces (47) and extending depthwise through the P-body layer (26) to at least a predetermined depth (56). Gate oxide (60) is formed on the trench walls and gate polysilicon (62) refills the trench to a level (64) near substrate upper surface (28). Oxide (68) between sidewall spacers (44) covers polysilicon (62). Removing the protective layer exposes upper substrate surface (28') between spacer inner surfaces (48). This area is doped to form a source layer (72) atop the body layer (26') and then trenched to form a second trench (80) having sidewalls aligned to the spacer inner surfaces. Second trench (80) defines vertically-oriented source and body layers (86, 90) stacked along gate oxide layer (60) to form vertical channels on opposite sides of second trench (80).

Title
High density power device fabrication process
Application Number
194874
Publication Number
5283201
Application Date
August 7, 1992
Publication Date
February 1, 1994
Inventor
Theodore O Meyer
Bend
OR, US
Douglas A Pike Jr
Bend
OR, US
John W Mosier II
Bend
OR, US
Dah W Tsang
Bend
OR, US
Agent
Marger Johnson McCollom & Stolowitz
Assignee
Advanced Power Technology
OR, US
IPC
H01L 21/265
H01L 21/02
H01L 21/00
View Original Source