05278974 is referenced by 18 patents and cites 21 patents.

The bandwidth of a first bus and a second bus, unequal due to differences in protocol overheads and cycle times between the buses, are equalized without sacrificing any bandwidth on the lower bandwidth bus and without introducing any buffering in a control logic device. The control logic device equalizes the bandwidths of the buses by instructing a device coupled to the second bus to insert a partial dead bus cycle in a read transmission thereby dynamically adjusting read timing on the second bus when the second bus is heavily loaded.

Title
Method and apparatus for the dynamic adjustment of data transfer timing to equalize the bandwidths of two buses in a computer system having different bandwidths
Application Number
7/445983
Publication Number
5278974
Application Date
December 4, 1989
Publication Date
January 11, 1994
Inventor
Jay C Stickney
Derry
NH, US
Raj Ramanujan
Leominster
MA, US
Paul J Lemmon
West Townsend
MA, US
Agent
Kenyon & Kenyon
Assignee
Digital Equipment Corporation
MA, US
IPC
G06F 13/14
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