05276848 is referenced by 118 patents and cites 14 patents.

A multilevel cache buffer for a multiprocessor system in which each processor has a level one cache storage unit which interfaces with a level two cache unit and main storage unit shared by all processors. The multiprocessors share the level two cache according to a priority algorithm. When data in the level two cache is updated, corresponding data in level one caches is invalidated until it is updated.

Title
Shared two level cache including apparatus for maintaining storage consistency
Application Number
212561
Publication Number
5276848
Application Date
August 20, 1991
Publication Date
January 4, 1994
Inventor
Stephen M Reeve
Endicott
NY, US
Steven L Gregor
Endicott
NY, US
Patrick W Gallagher
Vestal
NY, US
Agent
Hugh Jaeger
Pryor A Garnett
Arthur J Samodovitz
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 12/08
G06F 13/00
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