05265227 is referenced by 36 patents and cites 13 patents.

A translation look-aside buffer is implemented utilizing a four-way set associative cache memory having four lines of 16 sets each. A virtual address tag and its corresponding physical address tag, as well as a number of status bits which control the type of access permitted for a given virtual address, are stored in the translation look-aside buffer. A portion of the inputted virtual address signal is used to provide a virtual address tag and is compared to the virtual address tag in the buffer memory. When the virtual address tag comparison is achieved, the physical address tags are provided as an output from the translation look-aside buffer. Also at the same time, a fault detection circuit performs various fault detection logic on the status bits, depending on the execution cycle being performed, such as read/write cycle or user/supervisor mode. If a hit occurs with one of the stored virtual address tags, its physical address tag is used, but only if a fault indication does not occur thereby generating a trap. The comparison of the virtual address tags, the generation of the physical address tag and checking of the status bits for fault detection is performed simultaneously in parallel so that only one clock cycle is needed to generate a physical address tag and a fault signal, if any, from the address translation look-aside buffer.

Title
Parallel protection checking in an address translation look-aside buffer
Application Number
436368
Publication Number
5265227
Application Date
March 17, 1992
Publication Date
November 23, 1993
Inventor
Shai Rotem
Hoffit
IL
Leslie D Kohn
San Jose
CA, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Intel Corporation
CA, US
IPC
G06F 12/14
G06F 12/10
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