05256565 is referenced by 89 patents and cites 17 patents.

In a process for fabricating planarized thin film metal interconnects for integrated circuit structures, a planarized metal layer is etched back to the underlying dielectric layer by electropolishing, ion milling or other procedure. Electropolishing reduces processing time from hours to minutes and allows batch processing of multiple wafers. The etched back planarized thin film interconnect is flush with the dielectric layer.

Title
Electrochemical planarization
Application Number
7/348982
Publication Number
5256565
Application Date
May 8, 1989
Publication Date
October 26, 1993
Inventor
Robert J Contolini
Pleasanton
CA, US
Anthony F Bernhardt
Berkeley
CA, US
Agent
William R Moser
Roger S Gaither
Henry P Sartorio
Assignee
The United States of America represented by the United States Department of Energy
DC, US
IPC
H01L 21/465
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