05247655 is referenced by 79 patents and cites 43 patents.

A circuit for waking a microprocessor from a sleep mode and providing it with its microprocessor clock long enough for a refresh, direct memory access (DMA) or master cycle operation to be done by external circuitry. The clock signal is then removed from the microprocessor to put it back into the sleep mode, thereby conserving energy. A hold signal is provided to the microprocessor to cause the microprocessor outputs to be put into a tri-state, high impedance condition, and thus relinquish control of the external bus to the external refreshing circuitry.

Title
Sleep mode refresh apparatus
Application Number
7/432680
Publication Number
5247655
Application Date
November 7, 1989
Publication Date
September 21, 1993
Inventor
Aurav Gollabinnie
San Jose
CA, US
Win Sheng Cheng
Cupertino
CA, US
Brian Verstegen
Sunnyvale
CA, US
Chien Feng Cheng
Cupertino
CA, US
Cheng Chen
San Jose
CA, US
Rashid N Khan
Cupertino
CA, US
Agent
Townsend and Townsend Khourie and Crew
Assignee
Chips and Technologies
CA, US
IPC
G11C 1/00
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