05247626 is referenced by 82 patents and cites 5 patents.

A network interface interconnects a processor and a memory residing on a system bus having a predetermined average bus latency to a network containing other processors and memories. The interface, which is implemented using a bus master architecture, includes a network access controller for accessing data on the network, a random access memory, preferably in the form of an SRAM as a buffer between the network and system bus, and a network DMA controller. The Network Access Controller configures the buffer to have at least one logical FIFO for storing data; the size of the logical FIFO is related to the predetermined average bus latency. The DMA controller further controls transfer of data between the system memory and the network through the logical FIFOs. Preferably, the buffer is configured to have (1) a first logical FIFO for storing incoming data from the network and (2) at least one additional logical FIFO for storing outgoing data from said system memory to the network. Frames of data in the buffer are demarked by tag and status bits. The interface has particular utility in an FDDI type local area network.

FDDI controller having flexible buffer management
Application Number
Publication Number
Application Date
May 29, 1990
Publication Date
September 21, 1993
Farzin Firoozmand
Lowe Price LeBlanc & Becker
Advanced Micro Devices
H04L 12/00
G06F 13/00
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