05241636 is referenced by 100 patents and cites 3 patents.

A method for parallel instruction execution in a computer is described. If the computer is executing in the single-instruction mode and the computer encounters a first type of instruction with a dual-instruction mode bit having a first value, then one more single instruction is executed before dual-instruction mode instruction execution begins. The first type of instruction is an instruction having a dual-instruction mode bit. The dual-instruction mode instruction execution occurs in parallel. If the computer is executing in the dual-instruction mode and the computer encounters the first type of instruction with the dual-instruction mode bit having a second value, wherein the second value is different from the first value, then one more dual instruction is executed before single-instruction mode instruction execution resumes.

Title
Method for parallel instruction execution in a computer
Application Number
7/479946
Publication Number
5241636
Application Date
February 14, 1990
Publication Date
August 31, 1993
Inventor
Leslie D Kohn
San Jose
CA, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Intel Corporation
CA, US
IPC
G06F 9/30
G06F 9/22
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