05230068 is referenced by 102 patents and cites 32 patents.

A system which integrates the multiple instruction queues and the branch target cache (BTC) of a high performance CPU design into a single physical structure. Effectively, the queues are merged into the BTC in such a manner that, at any point in time, most of this structure functions as a BTC while certain entries function as instruction queues.

By using parts of the BTC to serve as instruction queues, the inefficiency of separate queue structures is eliminated and the queues are implemented with the greater device density characteristic of the RAM structure which the BTC core is based on. This merging of these structures also substantially simplifies the instruction queue control and the routing of instruction words between BTC entries and queues.

Title
Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence
Application Number
7/485304
Publication Number
5230068
Application Date
February 26, 1990
Publication Date
July 20, 1993
Inventor
John G Favor
San Jose
CA, US
David R Stiles
Sunnyvale
CA, US
Korbin S Van Dyke
Fremont
CA, US
Agent
Townsend and Townsend Khourie and Crew
Assignee
NexGen Microsystems
CA, US
IPC
G06F 9/30
G06F 12/08
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