05228134 is referenced by 84 patents and cites 8 patents.

An integrated circuit implements a cache static random access memory (SRAM) storage element which includes a central processor unit (CPU) bus interface incorporating multiplexers and buffers circuits for optimizing burst read and write operations across the CPU bus. Theses circuits allow a full cache line to be read/written in a single access of the SRAM array. Control logic is utilized within the CPU bus interface for controlling CPU bursts in the order defined by the CPU. The memory bus interface includes internal buffers used in performing memory bus reads, write-throughs, write-backs and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparently passing data between the CPU and memory bus interfaces without disturbance of the SRAM array.

Title
Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus
Application Number
7/710075
Publication Number
5228134
Application Date
June 4, 1991
Publication Date
July 13, 1993
Inventor
Robert L Farrell
Portland
OR, US
Clair C Webb
Aloha
OR, US
Peter D MacWilliams
Aloha
OR, US
Assignee
Intel Corporation
CA, US
IPC
G06F 12/28
G06F 12/08
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