05226130 is referenced by 260 patents and cites 21 patents.

The present invention provides for the updating of both the instructions in a branch prediction cache and instructions recently provided to an instruction pipeline from the cache when an instruction being executed attempts to change such instructions ("Store-Into-Instruction-Stream"). The branch prediction cache (BPC) includes a tag identifying the address of instructions causing a branch, a record of the target address which was branched to on the last occurrence of each branch instruction, and a copy of the first several instructions beginning at this target address. A separate instruction cache is provided for normal execution of instructions, and all of the instructions written into the branch prediction cache from the system bus must also be stored in the instruction cache. The instruction cache monitors the system bus for attempts to write to the address of an instruction contained in the instruction cache. Upon such a detection, that entry in the instruction cache is invalidated, and the corresponding entry in the branch prediction cache is invalidated. A subsequent attempt to use an instruction in the branch prediction cache which has been invalidated will detect that it is not valid, and will instead go to main memory to fetch the instruction, where it has been modified.

Title
Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
Application Number
7/485312
Publication Number
5226130
Application Date
February 26, 1990
Publication Date
July 6, 1993
Inventor
David R Stiles
Sunnyvale
CA, US
Korbin Van Dyke
Fremont
CA, US
John G Favor
San Jose
CA, US
Agent
Townsend and Townsend Khourie and Crew
Assignee
NexGen Microsystems
CA, US
IPC
G06F 9/42
G06F 9/38
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