05222223 is referenced by 81 patents and cites 14 patents.

In a pipelined computer system 10, memory access functions (requests) are simultaneously generated from a plurality of different locations. These multiple requests are passed through a multiplexer 50 according to a prioritization scheme based upon the operational proximity of the request to the instruction currently being executed. In this manner, the complex task of converting virtual-to-physical addresses is accomplished for all memory access requests by a single translation buffer 30. The physical address output from the translation buffer 30 are passed to a cache 28 through a second multiplexer 40 according to a second prioritization scheme based upon the operational proximity of the request to the instruction currently being executed. The first and second prioritization schemes differ, in that the memory is capable of handling other requests while a higher priority "miss" is pending. Thus, the prioritization scheme temporarily suspends the higher priority request while the desired data is being retrieved from main memory 14, but continues to operate on a lower priority request so that the overall operation will be enhanced if the lower priority request hits in the cache 28.

Title
Method and apparatus for ordering and queueing multiple memory requests
Application Number
7/306870
Publication Number
5222223
Application Date
February 3, 1989
Publication Date
June 22, 1993
Inventor
Dwight P Manley
Holliston
MA, US
Tryggve Fossum
Northboro
MA, US
John E Murray
Acton
MA, US
Ricky C Hetherington
Northboro
MA, US
David A Webb Jr
Berlin
MA, US
Agent
Arnold White & Durkee
Assignee
Digital Equipment Corporation
MA, US
IPC
G06F 12/00
G06F 13/16
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