05222030 is referenced by 102 patents and cites 7 patents.

A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure. The methodology includes using estimators, based on data gathered over a number of realized designs, for partitioning and evaluating a design prior to logic synthesis. From the structural description, a physical implementation of the device is readily realized.

Title
Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic specifications and descriptions thereof
Application Number
7/507201
Publication Number
5222030
Application Date
April 6, 1990
Publication Date
June 22, 1993
Inventor
Sreeranga P Rajan
Sunnyvale
CA, US
Ahsan Bootehsaz
Santa Clara
CA, US
Vijay K Nagasamy
Mountain View
CA, US
Carlos Dangelo
San Jose
CA, US
Agent
Michael D Rostoker
Gerald E Linden
Assignee
LSI Logic Corporation
CA, US
IPC
G06F 15/60
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