05218551 is referenced by 119 patents and cites 16 patents.

The invention is a method of designing an integrated circuit in which the steps of designing the circuit are optimized by a formal hierarchy. This method, called Timing Driven Placement, of designing an integrated circuit avoids detailed optimization which consumes enormous computational resources. It organizes physical and logical characteristics of the design so that those characteristics can be optimized with respect to the physical design of the circuit. The characteristics are optimized and the resulting circuit to location assignment is placed and wired with a conventional automated process. The method optimizes the global placement into precincts of logic segments of the circuit design with respect to the segment placement effect on circuit timing and wireability. The method then migrates individual circuits within particular segments to other segments to improve both the individual segment and overall circuit timing and wireability. Finally, the method transfers circuit assignment to logic segment and logic segment assignment to physical location information to a conventional process for final detailed circuit placement and wiring.

Title
Timing driven placement
Application Number
7/516944
Publication Number
5218551
Application Date
April 30, 1990
Publication Date
June 8, 1993
Inventor
Ralph W Wilk
Lakeville
CT, US
Cyril A Price
Stone Ridge
NY, US
Reini J Norman
Kingston
NY, US
Roger I McMillan
Newpulse
NY, US
Jerome M Kurtzberg
Yorktown Heights
NY, US
Joseph Hutt Jr
Poughkeepsie
NY, US
San Y Han
Poughkeepsie
NY, US
Wilm E Donath
Pleasantville
NY, US
Stephen E Bello
Kingston
NY, US
Bhuwan Agrawal
Chapel Hill
NC, US
Agent
George E Clark
Blaney Harper
Charles B Lobsenz
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 15/60
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