05210850 is referenced by 156 patents and cites 7 patents.

An apparatus for determining cacheable address and write-protect memory address regions in a computer system which includes a programmable single-ended limit register and a single comparator to determine each such region. A programmable limit register associated with each respective memory address region defines a boundary limit for each of the respective memory regions. A single address comparator associated with each respective limit register determines whether a memory address developed by the computer system resides between the respective boundaries provided by the value stored in the respective programmable limit register and a predefined address. The use of a single limit register and a single address comparator for each memory address region reduces the gate count and decreases the input buffer loading in the logic circuitry.

Title
Memory address space determination using programmable limit registers with single-ended comparators
Application Number
7/538724
Publication Number
5210850
Application Date
June 15, 1990
Publication Date
May 11, 1993
Inventor
Michael J Collins
Tomball
TX, US
Philip C Kelly
Houston
TX, US
Agent
Pravel Gambrell Hewitt Kimball & Krieger
Assignee
Compaq Computer Corporation
TX, US
IPC
G06F 12/14
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