05208491 is referenced by 356 patents and cites 12 patents.

A field programmable gate array (FPGA) comprising routing and logic blocks (RLBs) and segmented routing channels is disclosed. Each RLB is configurable to perform both logic functions and routing functions. A plurality of forwardly propagating RLBs (FPRLBs) and a plurality of backwardly propagating RLBs (BPRLBs) intermesh with one another to form a two-dimensional checkerboard array. Each column of the RLB array comprises a plurality of FPRLBs and BPRLBs in alternating sequence. Similarly, each row of the RLB array comprises a plurality of FPRLBs and BPRLBs in alternating sequence. The FPRLBs forwardly propagate signals and the BPRLBs backwardly propagate signals. Each FPRLB may receive a plurality of input signals from a plurality of FPRLBs in the preceding leftward column. Moreover, each FPRLB may output a plurality of output signals to a plurality of FPRLBs in the next rightward column. Similarly, each BPRLB may receive a plurality of input signals from a plurality of BPRLBs in the preceding rightward column and transmit a plurality of output signals to a plurality of BPRLBs in the next leftward column. A plurality of vertical segmented routing channels are disposed between the columns of RLBs, the vertical segmented routing channels accessible to the input and output of adjacent columns of RLBs.

Title
Field programmable gate array
Application Number
7/817697
Publication Number
5208491
Application Date
January 7, 1992
Publication Date
May 4, 1993
Inventor
Gaetano Borriello
Seattle
WA, US
William H C Ebeling
Seattle
WA, US
Agent
Christensen O Connor Johnson & Kindness
Assignee
Washington Research Foundation
WA, US
IPC
H01L 25/00
H03K 19/173
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