05195089 is referenced by 54 patents and cites 8 patents.

A high speed, synchronous, packet-switched inter-chip bus apparatus and method for transferring data between multiple system buses and a cache controller. In the preferred embodiment, the bus connects a cache controller client within the external cache of a processor to a plurality of bus watcher clients, each of which is coupled to a separate system bus. The bus allows the cache controller to provide independent processor-side access to the cache and allows the bus watchers to handle functions related to bus-snooping. An arbiter is employed to allow the bus to be multiplexed between the bus watchers and cache controller. Flow control mechanisms are also employed to ensure that queues receiving packets or arbitration requests over the bus never overflow. A default grantee mechanism is employed to minimize the arbitration latency due to a request for the bus when the bus is idle.

Title
Apparatus and method for a synchronous, high speed, packet-switched bus
Application Number
7/636446
Publication Number
5195089
Application Date
December 31, 1990
Publication Date
March 16, 1993
Inventor
Jean Marc Frailong
Palo Alto
CA, US
Jung Herng Chang
Saratoga
CA, US
Douglas B Lee
San Francisco
CA, US
Jorge Cruz Rios
Mountain View
CA, US
Bjorn Liencres
Palo Alto
CA, US
Pradeep S Sindhu
Mountain View
CA, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Sun Microsystems
CA, US
IPC
H04J 3/02
View Original Source