05193163 is referenced by 47 patents and cites 8 patents.

A method and apparatus for monitoring transactions on a system bus for invalidate requests, including a queue for storing the invalidate requests which is divided into two parts. The first part of the queue is contained within a cache controller to ensure that an invalidate request is immediately available for processing when the cache controller is otherwise idle. The second part of the queue is contained within a system interface to ensure that the system interface can detect and respond to more system transactions before the first invalidate request has been processed and to enable the system interface to be immediately aware if the entire queue is full.

Title
Two-level protocol for multi-component bus ownership, and implementation in a multi-processor cache write back protocol
Application Number
7/591197
Publication Number
5193163
Application Date
October 1, 1990
Publication Date
March 9, 1993
Inventor
Michael A Callander
Hudson
MA, US
Douglas E Sanders
Framingham
MA, US
Agent
Ronald Myrick
Barry Young
Denis G Maloney
Assignee
Digital Equipment Corporation
MA, US
IPC
G06F 13/00
G06F 12/00
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