05184320 is referenced by 74 patents and cites 8 patents.

A device for reducing access time to RAM arrays, especially DRAMs, by including fast access cache rows, e.g., four rows, to store data from accessed rows of the array, where data can then be accessed without precharging, row decoding sensing, and other cycling usually required to access the DRAM. Address registers, comparators, and MRU/LRU register and other cache control logic may be included in the device. The device allows parallel transfer of data between the RAM array and the cache rows. The device may be constructed on a single chip. A system is disclosed which makes use of the cache RAM features in a data processing system to take advantage of the attributes of a cache RAM memory.

Title
Cached random access memory device and system
Application Number
155668
Publication Number
5184320
Application Date
February 21, 1990
Publication Date
February 2, 1993
Inventor
Thomas A Dye
Cedar Park
TX, US
Agent
Richard L Donaldson
Robby T Holland
Lawrence J Bassuk
Assignee
Texas Instruments Incorporated
TX, US
IPC
G06F 12/00
G11C 15/04
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