05182754 is referenced by 3 patents and cites 7 patents.

A plurality of gates are arranged between a coincidence circuit and a group of comparators which compare data outputted by a processor's output buffers, and data inputted to the processor via terminals during a monitor mode. An invalid byte information generator is connected to the gates and applies a signal selected to mask the effects of write instructions being executed on an incomplete word and therefore prevents the generation of an erroneous mismatch signal.

Title
Microprocessor having improved functional redundancy monitor mode arrangement
Application Number
7/477051
Publication Number
5182754
Application Date
February 9, 1990
Publication Date
January 26, 1993
Inventor
Koji Maemura
Tokyo
JP
Yasuhiko Koumoto
Tokyo
JP
Agent
Foley & Lardner
Assignee
NEC Corporation
IPC
G06F 7/02
G06F 15/16
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