05165023 is referenced by 116 patents and cites 1 patents.

A highly-parallel processing system in which a number of processing elements are interconnected by a network, and are also connected to a system bus and are controlled by a central processing unit. Each processing element includes a memory, and all of the memories in the processing elements form at least part of the memory available to the CPU. The processing elements normally execute programs in MIMD mode, and the CPU or another unit can interrupt them to execute a SIMD instruction. The network allows for transmission of variable length messages and also for combining messages when received at a common processing element.

Title
Parallel processing system with processor array and network communications system for transmitting messages of variable length
Application Number
6/943375
Publication Number
5165023
Application Date
December 17, 1986
Publication Date
November 17, 1992
Inventor
David K Gifford
Cambridge
MA, US
Agent
Fish & richardson
Assignee
Massachusetts Institute of Technology
MA, US
IPC
G06F 15/80
G06F 13/00
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