05164325 is referenced by 109 patents and cites 16 patents.

A transistor constructed in accordance with our invention includes an N+ substrate, an N- region formed on the N+ substrate, a P- body region formed on the N- region, and an N+ source region formed on the P- body region. A vertical groove extends through the N+, P- and N- regions, and an insulating layer is formed on the groove walls. A polysilicon gate is formed inside the groove. Of importance, the portion of the insulating layer between the polysilicon and the N+ region and the insulating layer between the polysilicon and the N+ substrate is thicker than the portion of the insulating layer between the polysilicon gate and the P- body region. Because of the enhanced thickness of the portions of the insulating layer between the gate and N+ substrate, the transistor constructed in accordance with our invention is less susceptible to premature field induced breakdown.

Title
Method of making a vertical current flow field effect transistor
Application Number
7/107725
Publication Number
5164325
Application Date
October 8, 1987
Publication Date
November 17, 1992
Inventor
Richard A Blanchard
Los Altos
CA, US
Adrian I Cogan
San Jose
CA, US
Agent
Skjerven Morrill MacPherson Franklin & Friel
Assignee
Siliconix Incorporated
CA, US
IPC
H01L 21/70
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