05163140 is referenced by 100 patents and cites 21 patents.

An improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited number of branch instructions. The second direct mapped level BPC is a deep but narrow structure (256 2-byte entries), which caches only partial prediction information, but does so for a much larger number of branch instructions. As each branch instruction is fetched and decoded, its address is used to perform parallel look-ups in the two branch prediction caches.

Title
Two-level branch prediction cache
Application Number
485306
Publication Number
5163140
Application Date
March 2, 1992
Publication Date
November 10, 1992
Inventor
Korbin S Van Dyke
Fremont
CA, US
John G Favor
San Jose
CA, US
David R Stiles
Sunnyvale
CA, US
Agent
Townsend and Townsend
Assignee
Nexgen Microsystems
CA, US
IPC
G06F 12/08
G06F 12/00
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