The present invention provides a parallel memory scheduler for execution on a high speed highly parallel multiprocessor architecture. The operating system software provides intelligence and efficiency in swapping out process images to facilitate swapping in another process. The splitting and coalescing of data segments are used to fit segments in to current free memory even though a single contiguous space of sufficient size does not exist. Mapping these splits through data control register sets retains the user's contiguous view of the address space. The existence of dual images and partial swapping allows efficient, high speed swapping. Candidates for swap out are chosen in an intelligent fashion, selecting only those candidates which will most efficiently aLlow the swapin of another process.