05155824 is referenced by 103 patents and cites 10 patents.

A data cache capable of operation in a write-back (copyback) mode. The data cache design provides a mechanism for making the data cache coherent with memory, without writing the entire cache entry to memory, thereby reducing bus utilization. Each data cache entry is comprised of three items: data, a tag address, and a mixed size status field. The mixed size status fields provide one bit to indicate the validity of the data cache entry and multiple bits to indicate if the entry contains data that has not been written to memory (dirtiness). Multiple dirty bits provide a data cache controller with sufficient information to minimize the number of memory accesses used to unload a dirty entry. The data cache controller uses the multiple dirty bits to determine the quantity and type of accesses required to write the dirty data to memory. The portions of the entry being replaced that are clean (unmodified) are not written to memory.

Title
System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address
Application Number
7/351899
Publication Number
5155824
Application Date
May 15, 1989
Publication Date
October 13, 1992
Inventor
Russell A Reininger
Austin
TX, US
William B Ledbetter Jr
Austin
TX, US
Robin W Edenfield
Austin
TX, US
Agent
Charlotte B Whitaker
Assignee
Motorola
IL, US
IPC
G06F 7/10
G06F 12/12
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