05155816 is referenced by 128 patents and cites 14 patents.

A microprocessor having a pipelined architecture, an onchip data cache, a floating-point unit, a floating-point data latch and an instruction for accessing infrequently used data from an external memory system is disclosed. The instruction comprises a first-in-first-out memory for accumulating data in a pipeline manner, a first circuit means for coupling data from the external bus to the first-in-first-out memory and a second circuit means for transferring the data stored in the first-in-first-out memory to the floating-point data latch. The second circuit means also couples data from the cache to the first-in-first-out memory in the event of a cache hit. Finally, a bus control means is provided for controlling the orderly flow of data in accordance with the architecture of the microprocessor.

Title
Pipelined apparatus and method for controlled loading of floating point data in a microprocessor
Application Number
309429
Publication Number
5155816
Application Date
August 8, 1991
Publication Date
October 13, 1992
Inventor
Leslie D Kohn
San Jose
CA, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Intel Corporation
CA, US
IPC
G06F 12/08
G06F 13/00
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