05155432 is referenced by 41 patents and cites 13 patents.

The integrity of a circuit processing logic signals is verified by use of switching means, including pass transistors, which are selectively varied to provide different test circuit configurations for different modes of operation. The circuit operates in normal, scan, test and data receive modes. During normal operation, the logic signal from the primary circuit is passed directly through a logic test block without the shifting of data in the logic test block.

Title
System for scan testing of logic circuit networks
Application Number
106750
Publication Number
5155432
Application Date
July 16, 1991
Publication Date
October 13, 1992
Inventor
John E Mahoney
San Jose
CA, US
Agent
Edel M Young
Assignee
Xilinx
CA, US
IPC
G01R 31/28
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