A logic cell is described having four inputs, four outputs, a control store, means for multiplexing the four inputs onto two leads and logic means that operate in response to the signals on the two leads and signals from the control store to produce output signals which are applied to the four outputs. Illustrative logic functions provided by the logic means include a cross-over or identify function, a change in the routing direction of an input signal, NAND and XOR gates and a D-type flip-flop. The selection of two of the four inputs as well as the selection of the particular logic function that is implemented is controlled by control bits stored in the control store. Numerous such logic cells are arranged in a two-dimensional matrix such that each cell has four nearest neighbor cells, one to its left (or to the West) one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each one of the four inputs to a logic cell comes from a different one of that cell's four nearest neighbors and similarly each one of a cell's outputs is provided to a different one of that cell's four nearest neighbors. As a result of this arrangement, individual cells can be combined to produce blocks of cells that implement all manner of functions.