05134085 is referenced by 232 patents and cites 10 patents.

This invention constitutes a 10-12 mask, split-polysilicon process for fabricating dynamic random access memories of the stacked capacitor type for the one-megabit generation and beyond. The process flow is characterized: reduced mask count due to the elimination of the N+ and p+ source-drain masking layers via the split polysilicon technique; an option to further reduce wafer processing by allowing the LOCOS stress relief (pad) oxide layer to later function as the transistor gate dielectric layer; N-channel device optimization via self-aligned punch-through and lightly-doped-drain (LDD) implants, without the addition of extra P-channel masking steps via the split poly approach; use of semi, self-aligned contact of bottom cell plate to access gate diffusion allowing tight spacing between bottom cell plate buried contact and access gate polysilicon; improved refresh characteristics achieved by avoiding reduction of isolation thickness due to the spacer oxide etch; improved refresh characteristics achieved by protecting the sensitive areas of the storage node from damage typically caused by a spacer oxide etch; improved refresh characteristics achieved by eliminating the high-dose N-channel source/drain implantation from the storage node side of the access transistor gate; and improved immunity to soft error upset achieved through the use of an optional self-aligned "Hi-C" implant that is performed without the addition of an extra masking step.

Title
Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories
Application Number
7/796099
Publication Number
5134085
Application Date
November 21, 1991
Publication Date
July 28, 1992
Inventor
Anthony M McQueen
Boise
ID, US
Joseph J Karniewicz
Boise
ID, US
Tyler A Lowrey
Boise
ID, US
Brent D Gilgen
Boise
ID, US
Agent
Angus C Fox III
Assignee
Micron Technology
ID, US
IPC
H01L 21/70
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